Invention Grant
US08812761B2 System and method for adjusting power usage to reduce interrupt latency
有权
用于调整功耗的系统和方法,以减少中断延迟
- Patent Title: System and method for adjusting power usage to reduce interrupt latency
- Patent Title (中): 用于调整功耗的系统和方法,以减少中断延迟
-
Application No.: US13284746Application Date: 2011-10-28
-
Publication No.: US08812761B2Publication Date: 2014-08-19
- Inventor: Daniel S. Heller , Christopher G. Peak , Guy G. Sotomayor , Umesh S. Vaishampayan
- Applicant: Daniel S. Heller , Christopher G. Peak , Guy G. Sotomayor , Umesh S. Vaishampayan
- Applicant Address: US CA Cupertino
- Assignee: Apple Inc.
- Current Assignee: Apple Inc.
- Current Assignee Address: US CA Cupertino
- Agency: Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C.
- Main IPC: G06F13/24
- IPC: G06F13/24

Abstract:
A system and method are described for warming a processor from a low power state in anticipation of a time critical interrupt. For example, one embodiment of a method comprises: detecting that a time-critical interrupt will require processor resources at some point in the future; estimating a time at which the time-critical interrupt will be triggered; scheduling a timer interrupt to fire at a specified time prior to the estimated time that the time-critical interrupt will be triggered, the timer interrupt being scheduled with sufficient time to ensure that the processor is warmed to a level at which it is capable of handling the time-critical interrupt at the time that the time-critical interrupt is triggered; and responsively triggering the timer interrupt at the specified time prior to the time critical interrupt.
Public/Granted literature
- US20130111092A1 SYSTEM AND METHOD FOR ADJUSTING POWER USAGE TO REDUCE INTERRUPT LATENCY Public/Granted day:2013-05-02
Information query