A memory access management technique is disclosed, one embodiment of which relates to a technique to issue loads to a memory ahead of older store operations corresponding to the same target address. A processor may include load buffer entries having predictor table entries associated therewith, including saturation counters to record history of previous conflicts between loads and stores corresponding to the same target address. A watchdog unit may disable memory disambiguation (MD) if the MD causes too high a misprediction rate for load operation and store operation conflicts. In one embodiment, the MD is disabled if a flush counter value reaches a threshold.