Invention Grant
- Patent Title: Self-aligned via interconnect using relaxed patterning exposure
- Patent Title (中): 通过使用松弛图案曝光的互连自对准
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Application No.: US13550460Application Date: 2012-07-16
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Publication No.: US08813012B2Publication Date: 2014-08-19
- Inventor: Michael L. Rieger , Victor Moroz
- Applicant: Michael L. Rieger , Victor Moroz
- Applicant Address: US CA Mountain View
- Assignee: Synopsys, Inc.
- Current Assignee: Synopsys, Inc.
- Current Assignee Address: US CA Mountain View
- Agency: Fenwick & West LLP
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
Self-aligned via interconnects using relaxed patterning exposure. In accordance with a first method embodiment, a method for controlling a computer-aided design (CAD) system for designing physical features of an integrated circuit includes accessing a first pattern for first metal traces on a first metal layer, accessing a second pattern for second metal traces on a second metal layer, vertically adjacent to the first metal layer and accessing a precise pattern of intended interconnections between the first and second metal traces. The precise pattern of intended interconnections is operated on to form an imprecise via pattern that indicates a plurality of general areas in which vias are allowed. The imprecise via pattern is for use in an integrated circuit manufacturing process to form, in conjunction with operations to form the first and second metal layers, a plurality of self-aligned vias for interconnecting the intended interconnections.
Public/Granted literature
- US20140015135A1 SELF-ALIGNED VIA INTERCONNECT USING RELAXED PATTERNING EXPOSURE Public/Granted day:2014-01-16
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