Invention Grant
- Patent Title: Inclusion of chip elements in a sheathed wire
- Patent Title (中): 将芯片元件包含在护套电线中
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Application No.: US13703255Application Date: 2011-06-23
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Publication No.: US08814054B2Publication Date: 2014-08-26
- Inventor: Jean Brun , Laurent Lancon , Dominique Vicard
- Applicant: Jean Brun , Laurent Lancon , Dominique Vicard
- Applicant Address: FR Paris
- Assignee: Commissariat a l'Energie Atomique et Aux Energies Alternatives
- Current Assignee: Commissariat a l'Energie Atomique et Aux Energies Alternatives
- Current Assignee Address: FR Paris
- Agency: Oliff PLC
- Priority: FR1002656 20100624
- International Application: PCT/FR2011/000359 WO 20110623
- International Announcement: WO2011/161336 WO 20111229
- Main IPC: G06K19/06
- IPC: G06K19/06 ; D02G3/36 ; G06K19/077 ; H01L25/00 ; H01L23/00

Abstract:
A method for forming a sheathed wire includes the steps of: axially advancing a core through a sheathing zone; wrapping a sheathing fiber around the core in the sheathing zone; and providing, in the sheathing zone, a series of microelectronic chip elements each provided with a wire section, in such a way that the sheathing fiber that wraps around the core also wraps around a chip element and the wire section thereof to form a sheathed wire incorporating spaced-apart chip elements.
Public/Granted literature
- US20130092742A1 INCLUSION OF CHIP ELEMENTS IN A SHEATHED WIRE Public/Granted day:2013-04-18
Information query