Invention Grant
- Patent Title: Semiconductor constructions and methods of forming patterns
- Patent Title (中): 半导体结构和形成图案的方法
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Application No.: US13941747Application Date: 2013-07-15
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Publication No.: US08815497B2Publication Date: 2014-08-26
- Inventor: Dan Millward , Kaveri Jain , Zishu Zhang , Lijing Gou , Anton J. deVillers , Jianming Zhou , Yuan He , Michael Hyatt , Scott L. Light
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Wells St. John P.S.
- Main IPC: G03F7/26
- IPC: G03F7/26

Abstract:
Some embodiments include methods of forming patterns. A semiconductor substrate is formed to comprise an electrically insulative material over a set of electrically conductive structures. An interconnect region is defined across the electrically conductive structures, and regions on opposing sides of the interconnect region are defined as secondary regions. A two-dimensional array of features is formed over the electrically insulative material. The two-dimensional array extends across the interconnect region and across the secondary regions. A pattern of the two-dimensional array is transferred through the electrically insulative material of the interconnect region to form contact openings that extend through the electrically insulative material and to the electrically conductive structures, and no portions of the two-dimensional array of the secondary regions is transferred into the electrically insulative material.
Public/Granted literature
- US20130302981A1 Semiconductor Constructions And Methods Of Forming Patterns Public/Granted day:2013-11-14
Information query
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