Invention Grant
US08815675B2 Method of manufacturing nonvolatile semiconductor memory with backing wirings
有权
制造具有背衬布线的非易失性半导体存储器的方法
- Patent Title: Method of manufacturing nonvolatile semiconductor memory with backing wirings
- Patent Title (中): 制造具有背衬布线的非易失性半导体存储器的方法
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Application No.: US13324614Application Date: 2011-12-13
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Publication No.: US08815675B2Publication Date: 2014-08-26
- Inventor: Hideki Sugiyama , Hideki Hara
- Applicant: Hideki Sugiyama , Hideki Hara
- Applicant Address: JP Kanagawa
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Kanagawa
- Agency: Foley & Lardner LLP
- Priority: JP2006-168537 20060619
- Main IPC: H01L31/072
- IPC: H01L31/072

Abstract:
A nonvolatile semiconductor memory comprises a first memory cell transistor, a second memory cell transistor, a connection layer, protrusion portions and a contact portion. The first memory cell transistor comprises a first gate electrode formed above a first channel region, and a second gate electrode formed on a side of the first gate electrode through an insulating film. The second memory cell transistor comprises a third gate electrode formed above a second channel region, and a fourth gate electrode formed on a side of the third gate electrode through an insulating film and facing the second gate electrode. The connection layer connects the second gate electrode and the fourth gate electrode. The protrusion portions are formed of a material different than that of the second and fourth gate electrodes, and are formed on both ends of the connection layer. The contact portion is formed on the connection layer.
Public/Granted literature
- US20120083112A1 METHOD OF MANUFACTURING NONVOLATILE SEMICONDUCTOR MEMORY WITH BACKING WIRINGS Public/Granted day:2012-04-05
Information query
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