Invention Grant
- Patent Title: Methods for fabricating integrated circuits having confined epitaxial growth regions
- Patent Title (中): 制造具有有限外延生长区域的集成电路的方法
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Application No.: US13755246Application Date: 2013-01-31
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Publication No.: US08815685B2Publication Date: 2014-08-26
- Inventor: Nicholas LiCausi , Jody Fronheiser , Errol Todd Ryan
- Applicant: GLOBALFOUNDRIES, Inc.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES, Inc.
- Current Assignee: GLOBALFOUNDRIES, Inc.
- Current Assignee Address: KY Grand Cayman
- Agency: Ingrassia Fisher & Lorenz, P.C.
- Main IPC: H01L21/336
- IPC: H01L21/336 ; H01L21/762
Abstract:
Methods are provided for fabricating integrated circuits. In accordance with one embodiment, the method includes forming a portion of a semiconductor substrate at least partially bounded by a confinement isolation material. A liner dielectric is formed overlying the confinement isolation material and is treated to passivate a surface thereof. An epitaxial layer of semiconductor material is then grown overlying the portion of semiconductor substrate.
Public/Granted literature
- US20140213037A1 METHODS FOR FABRICATING INTEGRATED CIRCUITS HAVING CONFINED EPITAXIAL GROWTH REGIONS Public/Granted day:2014-07-31
Information query
IPC分类:
