Invention Grant
- Patent Title: Reducing pattern loading effect in epitaxy
- Patent Title (中): 降低外延图案加载效应
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Application No.: US13671243Application Date: 2012-11-07
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Publication No.: US08815713B2Publication Date: 2014-08-26
- Inventor: Hsueh-Chang Sung , Tsz-Mei Kwok , Kuan-Yu Chen , Kun-Mu Li
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater and Matsil, L.L.P.
- Main IPC: H01L21/20
- IPC: H01L21/20

Abstract:
A method includes forming a gate stack over a semiconductor substrate, forming an opening in the semiconductor substrate and adjacent to the gate stack, and performing a first epitaxy to grow a first semiconductor layer in the first opening. An etch-back is performed to reduce a thickness of the first semiconductor layer. A second epitaxy is performed to grow a second semiconductor layer over the first semiconductor layer. The first and the second semiconductor layers have different compositions.
Public/Granted literature
- US20140127886A1 Reducing Pattern Loading Effect in Epitaxy Public/Granted day:2014-05-08
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