Invention Grant
- Patent Title: Mosfet package
- Patent Title (中): Mosfet包装
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Application No.: US13906771Application Date: 2013-05-31
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Publication No.: US08816411B2Publication Date: 2014-08-26
- Inventor: Ryoichi Kajiwara , Masahiro Koizumi , Toshiak Morita , Kazuya Takahashi , Munehisa Kishimoto , Shigeru Ishii , Toshinori Hirashima , Yasushi Takahashi , Toshiyuki Hata , Hiroshi Sato , Keiichi Ookawa
- Applicant: Renesas Electronics Corporation , Renesas Eastern Japan Semiconductor, Inc.
- Applicant Address: JP Kanagawa JP Tokyo
- Assignee: Renesas Electronics Corporation,Renesas Eastern Japan Semiconductor, Inc.
- Current Assignee: Renesas Electronics Corporation,Renesas Eastern Japan Semiconductor, Inc.
- Current Assignee Address: JP Kanagawa JP Tokyo
- Agency: Antonelli, Terry, Stout & Kraus, LLP.
- Priority: JP11-19431 19990128; JP11-160539 19990608
- Main IPC: H01L29/94
- IPC: H01L29/94 ; H01R9/00 ; H01L21/00 ; H01L23/495 ; H01L23/31 ; H01L21/48 ; H05K3/34 ; H01L21/56 ; H01L29/78 ; H01L23/28
Abstract:
A semiconductor device featuring a semiconductor chip including a MOSFET and having a first main surface and a second, opposing main surface, a source electrode pad and a gate electrode pad over the first main surface, a drain electrode over the second main surface, a source external terminal and a gate external terminal, each having a first main surface electrically connected to the source electrode pad and gate electrode pad of the chip, respectively, and a drain external terminal having a first main surface and a second, opposing main surface and being electrically connected to the second main surface of the chip, each of the source, gate and drain external terminals having second main surfaces thereof in a same plane, and, in a plan view of the external terminals, the gate external terminal has a portion located between the source and drain external terminals in at least one direction.
Public/Granted literature
- US20130264696A1 SEMICONDUCTOR DEVICE Public/Granted day:2013-10-10
Information query
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