Invention Grant
- Patent Title: Checkerboarded high-voltage vertical transistor layout
- Patent Title (中): 棋盘式高压立式晶体管布局
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Application No.: US13852543Application Date: 2013-03-28
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Publication No.: US08816433B2Publication Date: 2014-08-26
- Inventor: Vijay Parthasarathy , Sujit Banerjee , Martin H. Manley
- Applicant: Power Integrations, Inc.
- Applicant Address: US CA San Jose
- Assignee: Power Integrations, Inc.
- Current Assignee: Power Integrations, Inc.
- Current Assignee Address: US CA San Jose
- Agency: The Law Offices of Bradley J. Bereznak
- Main IPC: H01L29/66
- IPC: H01L29/66

Abstract:
In one embodiment, a transistor fabricated on a semiconductor die includes a first section of transistor segments disposed in a first area of the semiconductor die, and a second section of transistor segments disposed in a second area of the semiconductor die adjacent the first area. Each of the transistor segments in the first and second sections includes a pillar of a semiconductor material that extends in a vertical direction. First and second dielectric regions are disposed on opposite sides of the pillar. First and second field plates are respectively disposed in the first and second dielectric regions. Outer field plates of transistor segments adjoining first and second sections are either separated or partially merged.
Public/Granted literature
- US20130234243A1 Checkerboarded High-Voltage Vertical Transistor Layout Public/Granted day:2013-09-12
Information query
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