Invention Grant
- Patent Title: Low noise and high performance LSI device
- Patent Title (中): 低噪声,高性能的LSI器件
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Application No.: US12984261Application Date: 2011-01-04
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Publication No.: US08816440B2Publication Date: 2014-08-26
- Inventor: Shigenobu Maeda , Jeong Hwan Yang
- Applicant: Shigenobu Maeda , Jeong Hwan Yang
- Applicant Address: KR
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR
- Agency: Myers Bigel Sibley & Sajovec
- Priority: KR2004-0021569 20040330
- Main IPC: H01L29/94
- IPC: H01L29/94 ; H01L31/062 ; H01L31/113

Abstract:
In semiconductor devices in which both NMOS devices and PMOS devices are used to perform in different modes such as analog and digital modes, stress engineering is selectively applied to particular devices depending on their required operational modes. That is, the appropriate mechanical stress, i.e., tensile or compressive, can be applied to and/or removed from devices, i.e., NMOS and/or PMOS devices, based not only on their conductivity type, i.e., n-type or p-type, but also on their intended operational application, for example, analog/digital, low-voltage/high-voltage, high-speed/low-speed, noise-sensitive/noise-insensitive, etc. The result is that performance of individual devices is optimized based on the mode in which they operate. For example, mechanical stress can be applied to devices that operate in high-speed digital settings, while devices that operate in analog or RF signal settings, in which electrical noise such as flicker noise that may be introduced by applied stress may degrade performance, have no stress applied.
Public/Granted literature
- US20110147852A1 LOW NOISE AND HIGH PERFORMANCE LSI DEVICE, LAYOUT AND MANUFACTURING METHOD Public/Granted day:2011-06-23
Information query
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