Invention Grant
US08816715B2 MOS test structure, method for forming MOS test structure and method for performing wafer acceptance test
有权
MOS测试结构,用于形成MOS测试结构的方法和用于进行晶片验收测试的方法
- Patent Title: MOS test structure, method for forming MOS test structure and method for performing wafer acceptance test
- Patent Title (中): MOS测试结构,用于形成MOS测试结构的方法和用于进行晶片验收测试的方法
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Application No.: US13105913Application Date: 2011-05-12
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Publication No.: US08816715B2Publication Date: 2014-08-26
- Inventor: Chin-Te Kuo , Yi-Nan Chen , Hsien-Wen Liu
- Applicant: Chin-Te Kuo , Yi-Nan Chen , Hsien-Wen Liu
- Applicant Address: TW Kueishan, Tao-Yuan Hsien
- Assignee: Nanya Technology Corp.
- Current Assignee: Nanya Technology Corp.
- Current Assignee Address: TW Kueishan, Tao-Yuan Hsien
- Agent Winston Hsu; Scott Margo
- Main IPC: G01R31/02
- IPC: G01R31/02 ; G01R31/26 ; H01L21/66 ; G01R31/28

Abstract:
A MOS test structure is disclosed. A scribe line region is disposed on a substrate which has a first side and a second side opposite to the first side. An epitaxial layer is disposed on the first side, the doping well is disposed on the epitaxial layer and the doping region is disposed on the doping well. A trench gate of a first depth is disposed in the doping region, in the doping well and in the scribe line region. A conductive material fills the test via which has a second depth and an isolation covering the inner wall of the test via and is disposed in the doping region, in the doping well, in the epitaxial layer and in the scribe line region, to electrically connect to the epitaxial layer so that the test via is capable of testing the epitaxial layer and the substrate together.
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