A semiconductor memory device includes a memory cell array having a plurality of memory cells arranged in a matrix, each memory cell being configured such that a variable resistance element and a selection transistor are connected in series. A set operation for a memory cell (an operation of converting the resistance of the variable resistance element to a low resistance) is performed by applying a set voltage pulse for a longer time than that for a reset operation (an operation of converting the resistance of the variable resistance element to a high resistance) while limiting, using the selection transistor, an electric current flowing in the set operation to a certain low electric current, and by simultaneously applying the set voltage pulse to the plurality of memory cells.