Invention Grant
- Patent Title: Data-masked analog and digital read for resistive memories
- Patent Title (中): 数据屏蔽模拟和数字读取电阻存储器
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Application No.: US13657002Application Date: 2012-10-22
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Publication No.: US08817530B2Publication Date: 2014-08-26
- Inventor: Syed M. Alam , Thomas Andre
- Applicant: Everspin Technologies, Inc.
- Applicant Address: US AZ Chandler
- Assignee: EverSpin Technologies, Inc.
- Current Assignee: EverSpin Technologies, Inc.
- Current Assignee Address: US AZ Chandler
- Agency: Ingrassia Fisher & Lorenz, P.C.
- Main IPC: G11C7/10
- IPC: G11C7/10 ; G11C7/00 ; G11C7/12 ; G11C11/00 ; G11C11/16 ; G11C11/02 ; G11C13/00
Abstract:
An analog read circuit measures the resistance of each of a plurality of bits in an array of resistive memory elements. Data stored within a latch determines whether to selectively enable the analog read circuit. In an alternate embodiment, a sense amplifier is coupled to the latch and the array, and the data stored in the latch determines whether to selectively enable the sense amplifier.
Public/Granted literature
- US20130128650A1 DATA-MASKED ANALOG AND DIGITAL READ FOR RESISTIVE MEMORIES Public/Granted day:2013-05-23
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