Provided is a readout circuit for a non-volatile memory device, which has a large readout margin for distinguishing between 0 and 1 of data and has a small circuit area. A voltage output from a single bias circuit is applied to a gate of a memory element and a gate of an NMOS transistor serving as a reference current source to be compared with a current flowing through the memory element. Thus, the gates are controlled by the same voltage, and hence characteristics fluctuations in the operating temperature range and the operating power supply voltage range are reduced. Therefore, a large readout margin for distinguishing 0 and 1 of data can be obtained, resulting in a simplified circuit configuration.