A system and method for designing a field programmable gate array (FPGA) with built-in test mechanism includes several enhancements to traditional circular self-test path (CSTP) BIST architecture. The FPGA BIST scheme isolates primary inputs and primary outputs to improve test coverage. Multiple signature output taps are inserted at CSTP registers throughout the test path to help improve signature aliasing probability. Enhanced CSTP register selection algorithms help prevent register adjacency problems and optimize overall resource utilization for implementation. Multiple clock domains are also handled by the FPGA BIST to allow full chip implementation of the FPGA BIST.