Invention Grant
- Patent Title: Dual lead frame semiconductor package and method of manufacture
- Patent Title (中): 双引线框半导体封装及其制造方法
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Application No.: US13229667Application Date: 2011-09-09
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Publication No.: US08822273B2Publication Date: 2014-09-02
- Inventor: Frank Kuo , Suresh Belani
- Applicant: Frank Kuo , Suresh Belani
- Applicant Address: US CA Santa Clara
- Assignee: Vishay-Siliconix
- Current Assignee: Vishay-Siliconix
- Current Assignee Address: US CA Santa Clara
- Priority: TW99730417A 20100909
- Main IPC: H01L29/72
- IPC: H01L29/72
Abstract:
A semiconductor package and a method for making the same are provided. In the method, a clip is used to conduct a lead frame and at least one chip. The clip has at least one second connection segment, at least one third connection segment, and at least one intermediate connection segment. The second connection segment is electrically connected to a second conduction region of the chip and a second pin of the lead frame respectively, and the third connection segment is electrically connected to a third conduction region of the chip and a third pin of the lead frame respectively. The intermediate connection segment connects the at least one second connection segment and the at least one third connection segment, and is removed in a subsequent process. Thereby, the present invention does not need to use any gold wire, which effectively saves the material cost and the processing time.
Public/Granted literature
- US20120112331A1 Dual Lead Frame Semiconductor Package and Method of Manufacture Public/Granted day:2012-05-10
Information query
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