Invention Grant
US08822282B2 Methods of fabricating contact regions for FET incorporating SiGe
有权
制造结合SiGe的FET的接触区域的方法
- Patent Title: Methods of fabricating contact regions for FET incorporating SiGe
- Patent Title (中): 制造结合SiGe的FET的接触区域的方法
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Application No.: US10854556Application Date: 2004-05-26
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Publication No.: US08822282B2Publication Date: 2014-09-02
- Inventor: Eugene A. Fitzgerald
- Applicant: Eugene A. Fitzgerald
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater and Matsil, L.L.P.
- Main IPC: H01L29/72
- IPC: H01L29/72

Abstract:
Structures and methods for fabricating high speed digital, analog, and combined digital/analog systems using planarized relaxed SiGe as the materials platform. The relaxed SiGe allows for a plethora of strained Si layers that possess enhanced electronic properties. By allowing the MOSFET channel to be either at the surface or buried, one can create high-speed digital and/or analog circuits. The planarization before the device epitaxial layers are deposited ensures a flat surface for state-of-the-art lithography.
Public/Granted literature
- US20040219726A1 Methods of fabricating contact regions for FET incorporating SiGe Public/Granted day:2004-11-04
Information query
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