Invention Grant
US08822298B2 Performance enhancement in transistors by reducing the recessing of active regions and removing spacers
有权
通过减少活性区域的凹陷和去除间隔物来提高晶体管的性能
- Patent Title: Performance enhancement in transistors by reducing the recessing of active regions and removing spacers
- Patent Title (中): 通过减少活性区域的凹陷和去除间隔物来提高晶体管的性能
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Application No.: US13421242Application Date: 2012-03-15
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Publication No.: US08822298B2Publication Date: 2014-09-02
- Inventor: Stefan Flachowsky , Jan Hoentschel
- Applicant: Stefan Flachowsky , Jan Hoentschel
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee Address: KY Grand Cayman
- Agency: Amerson Law Firm, PLLC
- Priority: DE102011005641 20110316
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L21/8238 ; H01L21/8234
Abstract:
Sophisticated transistors for semiconductor devices may be formed on the basis of a superior process sequence in which an increased space between closely spaced gate electrode structures may be obtained in combination with a reduced material loss in the active regions. To this end, an offset spacer conventionally used for laterally profiling the drain and source extension regions is omitted and the spacer for the deep drain and source areas may be completely removed.
Public/Granted literature
- US20120235215A1 PERFORMANCE ENHANCEMENT IN TRANSISTORS BY REDUCING THE RECESSING OF ACTIVE REGIONS AND REMOVING SPACERS Public/Granted day:2012-09-20
Information query
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