Method to reduce depth delta between dense and wide features in dual damascene structures

Invention Grant

US08822342B2 Method to reduce depth delta between dense and wide features in dual damascene structures 有权

Title translation: 减少双重镶嵌结构密集和宽特征之间深度三角洲的方法

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Patent Title: Method to reduce depth delta between dense and wide features in dual damascene structures
Patent Title (中): 减少双重镶嵌结构密集和宽特征之间深度三角洲的方法
Application No.: US12981519

Application Date: 2010-12-30
Publication No.: US08822342B2

Publication Date: 2014-09-02
Inventor: Ravi Prakash Srivastava , Oluwafemi. O. Ogunsola , Craig Child , Muhammed Shafi Kurikka Valappil Pallachalil , Habib Hichri , Matthew Angyal , Hideshi Miyajima
Applicant: Ravi Prakash Srivastava , Oluwafemi. O. Ogunsola , Craig Child , Muhammed Shafi Kurikka Valappil Pallachalil , Habib Hichri , Matthew Angyal , Hideshi Miyajima
Applicant Address: SG Singapore
Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.,International Business Machines Corporation,Advanced Micro Devices Corporation,Infineon Technologies North America Corp.,Toshiba America Electronic Components, Inc.
Current Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.,International Business Machines Corporation,Advanced Micro Devices Corporation,Infineon Technologies North America Corp.,Toshiba America Electronic Components, Inc.
Current Assignee Address: SG Singapore
Agency: Horizon IP Pte. Ltd.
Main IPC: H01L21/311
IPC: H01L21/311 ; H01L21/768

Method to reduce depth delta between dense and wide features in dual damascene structures

Abstract:

A method of forming a device is disclosed. The method includes providing a substrate prepared with a dielectric layer having first and second regions. The first region comprises wide features and the second region comprises narrow features. A depth delta exists between bottoms of the wide and narrow features. A non-conformal layer is formed on the substrate and it lines the wide and narrow trenches in the first and second regions. The non-conformal layer is removed. Removing the non-conformal layer reduces the depth delta between the bottoms of the wide and narrow features in the first and second region.

Abstract(Chinese):

公开了一种形成装置的方法。该方法包括提供用具有第一和第二区域的电介质层制备的衬底。第一区域包括宽的特征，第二区域包括狭窄的特征。在宽和窄特征的底部之间存在深度增量。在基板上形成非保形层，并且在第一和第二区域中对宽且窄的沟槽进行排列。去除非保形层。去除非保形层减少了第一和第二区域中宽和窄特征的底部之间的深度增量。

Public/Granted literature

US20120168957A1 METHOD TO REDUCE DEPTH DELTA BETWEEN DENSE AND WIDE FEATURES IN DUAL DAMASCENE STRUCTURES Public/Granted day:2012-07-05

Information query

Espacenet

IPC分类:

H	电学
H01	基本电气元件
H01L	半导体器件；其他类目中不包括的电固体器件（使用半导体器件的测量入G01；一般电阻器入H01C；磁体、电感器、变压器入H01F；一般电容器入H01G；电解型器件入H01G9/00；电池组、蓄电池入H01M；波导管、谐振器或波导型线路入H01P；线路连接器、汇流器入H01R；受激发射器件入H01S；机电谐振器入H03H；扬声器、送话器、留声机拾音器或类似的声机电传感器入H04R；一般电光源入H05B；印刷电路、混合电路、电设备的外壳或结构零部件、电气元件的组件的制造入H05K；在具有特殊应用的电路中使用的半导体器件见应用相关的小类）
H01L21/00	专门适用于制造或处理半导体或固体器件或其部件的方法或设备
H01L21/02	.半导体器件或其部件的制造或处理
H01L21/04	..至少具有一个跃变势垒或表面势垒的器件，例如PN结、耗尽层、载体集结层
H01L21/18	...器件有由周期表Ⅳ族元素或含有/不含有杂质的AⅢBⅤ族化合物构成的半导体，如掺杂材料
H01L21/30	....用H01L21/20至H01L21/26各组不包含的方法或设备处理半导体材料的（在半导体材料上制作电极的入H01L21/28）
H01L21/31	.....在半导体材料上形成绝缘层的，例如用于掩膜的或应用光刻技术的（密封层入H01L21/56）；以及这些层的后处理；这些层的材料的选择
H01L21/3105	......后处理
H01L21/311	.......绝缘层的刻蚀