Invention Grant
US08823064B2 Asymmetric FET formed through use of variable pitch gate for use as logic device and test structure
有权
通过使用可变间距门形成的非对称FET用作逻辑器件和测试结构
- Patent Title: Asymmetric FET formed through use of variable pitch gate for use as logic device and test structure
- Patent Title (中): 通过使用可变间距门形成的非对称FET用作逻辑器件和测试结构
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Application No.: US13441048Application Date: 2012-04-06
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Publication No.: US08823064B2Publication Date: 2014-09-02
- Inventor: Josephine B. Chang , Chung-Hsun Lin , Isaac Lauer , Jeffrey W. Sleight
- Applicant: Josephine B. Chang , Chung-Hsun Lin , Isaac Lauer , Jeffrey W. Sleight
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Michael J. Chang, LLC
- Agent Vazken Alexanian
- Main IPC: H01L27/12
- IPC: H01L27/12
Abstract:
Asymmetric FET devices and methods for fabrication thereof that employ a variable pitch gate are provided. In one aspect, a FET device is provided. The FET device includes a wafer; a plurality of active areas formed in the wafer; a plurality of gate stacks on the wafer, wherein at least one of the gate stacks is present over each of the active areas, and wherein the gate stacks have an irregular gate-to-gate spacing such that for at least a given one of the active areas a gate-to-gate spacing on a source side of the given active area is greater than a gate-to-gate spacing on a drain side of the given active area; spacers on opposite sides of the gate stacks; and an angled implant in the source side of the given active area.
Public/Granted literature
- US20130256797A1 Asymmetric FET Formed Through Use of Variable Pitch Gate for Use as Logic Device and Test Structure Public/Granted day:2013-10-03
Information query
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