Invention Grant
- Patent Title: Latch-up prevention structure and method for ultra-small high voltage tolerant cell
- Patent Title (中): 超小型耐高压电池的锁定防止结构和方法
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Application No.: US12797782Application Date: 2010-06-10
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Publication No.: US08823129B2Publication Date: 2014-09-02
- Inventor: Da-Wei Lai , Jen-Chou Tseng , Chien-Yuan Lee
- Applicant: Da-Wei Lai , Jen-Chou Tseng , Chien-Yuan Lee
- Applicant Address: TW
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW
- Agency: Lowe Hauptman & Ham, LLP
- Main IPC: H01L27/105
- IPC: H01L27/105 ; H01L27/092 ; H01L29/06 ; H01L27/118

Abstract:
A latch-up prevention structure and method for ultra-small high voltage tolerant cell is provided. In one embodiment, the integrated circuit includes an input and/or output pad, a floating high-voltage n-well (HVNW) connected to the input and/or output pad through a P+ in the floating HVNW and also connected to a first voltage supply, a low-voltage n-well (LVNW) connected to a second voltage supply through a N+ in the LVNW, a HVNW control circuit, and a guard-ring HVNW, where the first voltage supply has higher voltage level than the second voltage supply, guard-ring HVNW is inserted in between the floating HVNW and LVNW to prevent a latch-up path between a P+ in HVNW and N+ in LVNW by using the HVNW control circuit that controls the guard-ring HVNW's voltage level. The guard-ring HVNW's voltage level is matched by the floating HVNW's voltage level.
Public/Granted literature
- US20100314709A1 LATCH-UP PREVENTION STRUCTURE AND METHOD FOR ULTRA-SMALL HIGH VOLTAGE TOLERANT CELL Public/Granted day:2010-12-16
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