Invention Grant
- Patent Title: Apparatus and method for three dimensional integrated circuits
- Patent Title (中): 三维集成电路的装置和方法
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Application No.: US13706436Application Date: 2012-12-06
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Publication No.: US08823170B2Publication Date: 2014-09-02
- Inventor: Sheng-Yu Wu , Pei-Chun Tsai , Chih-Horng Chang , Tin-Hao Kuo , Chen-Shien Chen
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater and Matsil, L.L.P.
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L21/50 ; H01L23/498
Abstract:
A structure comprises a substrate comprising a plurality of traces on top of the substrate, a plurality of connectors formed on a top surface of a semiconductor die, wherein the semiconductor die is formed on the substrate and coupled to the substrate through the plurality of connectors and a dummy metal structure formed at a corner of a top surface of the substrate, wherein the dummy metal structure has two discontinuous sections.
Public/Granted literature
- US20140159232A1 Apparatus and Method for Three Dimensional Integrated Circuits Public/Granted day:2014-06-12
Information query
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