A semiconductor package includes a semiconductor chip, a first insulating layer formed to cover the semiconductor chip, a wiring structure formed on the first insulating layer. The wiring structure has an alternately layered configuration including wiring layers electrically connected to the semiconductor chip and interlayer insulating layers each located between one of the wiring layers and another. The interlayer insulating layers include an outermost interlayer insulating layer located farthest from a surface of the first insulating layer. A groove formed in the outermost interlayer insulating layer passes through the outermost interlayer insulating layer in a thickness direction.