Invention Grant
US08823343B2 Power amplifying circuit, DC-DC converter, peak holding circuit, and output voltage control circuit including the peak holding circuit
有权
功率放大电路，DC-DC转换器，峰值保持电路和包括峰值保持电路的输出电压控制电路
- Patent Title: Power amplifying circuit, DC-DC converter, peak holding circuit, and output voltage control circuit including the peak holding circuit
- Patent Title (中): 功率放大电路，DC-DC转换器，峰值保持电路和包括峰值保持电路的输出电压控制电路
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Application No.: US12928825Application Date: 2010-12-20
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Publication No.: US08823343B2Publication Date: 2014-09-02
- Inventor: Nobuaki Tsuji
- Applicant: Nobuaki Tsuji
- Applicant Address: JP Hamamatsu-shi
- Assignee: Yamaha Corporation
- Current Assignee: Yamaha Corporation
- Current Assignee Address: JP Hamamatsu-shi
- Agency: Pillsbury Winthrop Shaw Pittman LLP
- Priority: JP2009-291350 20091222; JP2009-291501 20091222; JP2009-293998 20091225; JP2009-294003 20091225
- Main IPC: G05F1/00
- IPC: G05F1/00
Abstract:
A power amplifying circuit includes a first field effect transistor and a second field effect transistor that are connected in series, are interposed between a high potential power line and a low potential power line, and drive a load; a predriver that generates, in response to an input signal, gate voltages applied to the first field effect transistor and the second field effect transistor respectively; and a variable power source that supplies source voltages to the high potential power line and the low potential power line respectively, and is configured to control the source voltages.
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