Embodiments may comprise logic such as hardware and/or code for high-speed digital-to-analog conversion of signals. Many embodiments comprise a demultiplexer to distribute sets of bits to digital-to-analog converters, the digital-to-analog converters to receive the sets of bits and the operate concurrently to convert the sets of bits from digital representations of signal segments to output analog signal segments, and an interleaver to interleave the analog signal segments from each of digital-to-analog converters in the sequence to generate an analog signal. In many embodiments, the interleaver is adapted to interleave the analog signal segments by latching magnitudes of each of the analog signal segments to an interleaved output near ends of clock cycles to attenuate non-linearities in the magnitudes of each of the analog signal segments when the magnitudes are output.