Invention Grant
- Patent Title: Graphics tiling architecture with bounding volume hierarchies
- Patent Title (中): 具有界限体积层次结构的图形拼接体系结构
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Application No.: US13354712Application Date: 2012-01-20
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Publication No.: US08823736B2Publication Date: 2014-09-02
- Inventor: Rasmus Barringer , Carl Johan Gribel , Aaron Lefohn , Tomas G. Akenine-Möller
- Applicant: Rasmus Barringer , Carl Johan Gribel , Aaron Lefohn , Tomas G. Akenine-Möller
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Trop, Pruner & Hu, P.C
- Main IPC: G09G5/00
- IPC: G09G5/00

Abstract:
In some embodiments, tile lists may be avoided by storing the geometry of a scene in a bounding volume hierarchy (BVH). For each tile, the bounding volume hierarchy is traversed. The traversals continued only into children nodes that overlap with the frustum on the tile. By relaxing the ordering constraint of rendering primitives, the BVH is traversed such that nodes that are closer to the viewer are traversed first, increasing the occlusion culling efficiency in some embodiments. Rendering the full scene between the central processing cores and the graphics processor may be done through a shared memory in some embodiments.
Public/Granted literature
- US20130187947A1 Graphics Tiling Architecture With Bounding Volume Hierarchies Public/Granted day:2013-07-25
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