A semiconductor memory apparatus includes: a read current supply unit configured to supply a read current; a resistive memory cell configured to pass a current having a magnitude corresponding to a resistance value thereof in a data read mode; a voltage transfer unit coupled between the read current supply unit and the resistive memory cell and configured to transfer the read current to the resistive memory cell, wherein a voltage corresponding to the magnitude of the passed current is formed at a sensing node; and a feedback unit configured to pull-down drive a connection node, which is coupled between the voltage transfer unit and the resistive memory cell, when a voltage level of the sensing node reaches a predefined level.