A semiconductor memory device may include a cell string configured to include memory cells, a page buffer coupled to the cell string through a bit line, and configured to include a latch for storing data to be programmed in a memory cell or data read from the memory cell, a precharge voltage generation circuit configured to generate a precharge voltage from an external voltage according to the data stored in the latch, bit line precharge circuits configured to supply the precharge voltage to the bit line in response to precharge control signals, and a control circuit configured to output the precharge control signals so that the number of enabled bit line precharge circuits increases, accordingly, as a supply number of a program voltage augments in a program operation.