A packet communication device for communicating a packet to be transferred in constant cycle, comprising one of a logic inversion section configured to invert a logical value with respect to at least one bit included in a first string of bits included in a first packet; and a register section configured to store another string of bits having a logical value different from a given logical value of the first string of bits; and a selector section configured to select one of the first string of bits and a second string of bits that is output from one of the logic inversion section and the register section to designate any one of a plurality of devices, wherein the packet communication is performed when a selected string of bits selected by the selector section conforms to a setting value of a receiving side.