Invention Grant
- Patent Title: Buffer circuit and buffer circuit driving method
- Patent Title (中): 缓冲电路和缓冲电路驱动方法
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Application No.: US13735354Application Date: 2013-01-07
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Publication No.: US08824622B2Publication Date: 2014-09-02
- Inventor: Hitoshi Tsuge , Masafumi Matsui
- Applicant: Panasonic Corporation
- Applicant Address: JP Osaka
- Assignee: Panasonic Corporation
- Current Assignee: Panasonic Corporation
- Current Assignee Address: JP Osaka
- Agency: Greenblum & Bernstein, P.L.C.
- Main IPC: G11C19/00
- IPC: G11C19/00 ; H03K3/00 ; G11C19/18 ; G11C19/28

Abstract:
A buffer circuit driving method for driving a buffer circuit including: an output terminal; a first transistor connected to a signal source of a clock signal that is of at least a first voltage or a second voltage lower than the first voltage, for supplying the first voltage to the output terminal; and a second transistor connected to a voltage source that supplies a third voltage lower than the first voltage, for supplying the third voltage to the output terminal, includes: causing the first transistor to switch to a conducting state in a period where the clock signal is of the first voltage; and causing the first transistor and the second transistor to switch to the conducting state in a period where the clock signal is of the second voltage, following the period where the clock signal is of the first voltage.
Public/Granted literature
- US20130266113A1 BUFFER CIRCUIT AND BUFFER CIRCUIT DRIVING METHOD Public/Granted day:2013-10-10
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