The present disclosure includes systems and techniques relating to non-volatile memory. A described system, for example, includes a non-volatile memory structure having a plurality of multi-level memory cells, a processing device, and a controller. The controller is configured to map a first portion of a first set of consecutive bits of a data segment to a first page associated with the plurality of multi-level memory cells, and map a second portion of the first set of consecutive bits of the data segment to a second page associated with the plurality of multi-level memory cells. The first page is associated with bits of a first significance, and the second page is associated with bits of a second significance.