A method for producing a verified design of a digital to analog converter (DAC) starts with providing an HDL representation of the DAC. Numerical values of the analog output signal as a function of the representation of the DAC for a range of numerical values of the digital input signal are simulated with a simulator. A model is used for converting the simulated numerical values of the analog output signal to numerical values of an equivalent model signal in the same digital format as the input signal. A comparator compares the numerical values of the input signal and the model signal and determines differences greater than a defined tolerance.