Defect characterization is a useful tool for analyzing and improving fabrication for semiconductor chips. By using layout and netlist in combination with images of semiconductors, defects can be identified and analyzed. Electrical simulation can be performed on the netlist, based on the presence of the defect that was detected. Layout geometries where the defect was detected can be binned and a search can be performed of the remainder of the layout for similar groupings of layout geometries. Various representations of the semiconductor can be cross mapped, including layout, schematic, and netlist. The presence of certain defects can be correlated to yield, performance, and other characteristics.