In one embodiment of the invention, a method for displaying and analyzing a clock gate tree topology is disclosed. The method includes displaying a bounding box of each flip-flop cluster in the floor plan of the integrated circuit; and for each flip-flop cluster, calculating the coordinates for a center of mass of the flip-flop cluster, displaying the position of the clock gate driving the flip-flops in the flip-flop cluster with respect to the center of mass of the flip-flop cluster, displaying first air lines from the enable signal gate to the clock gate with a first color, and displaying second air lines from the clock gate to the center of mass of the flip-flop cluster with a second color differing from the first color.