Invention Grant
US08828825B2 Method of substantially reducing the formation of SiGe abnormal growths on polycrystalline electrodes for strained channel PMOS transistors
有权
在应变通道PMOS晶体管的多晶电极上大大减少SiGe异常生长的形成的方法
- Patent Title: Method of substantially reducing the formation of SiGe abnormal growths on polycrystalline electrodes for strained channel PMOS transistors
- Patent Title (中): 在应变通道PMOS晶体管的多晶电极上大大减少SiGe异常生长的形成的方法
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Application No.: US13550494Application Date: 2012-07-16
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Publication No.: US08828825B2Publication Date: 2014-09-09
- Inventor: Hiroaki Niimi , James Joseph Chambers
- Applicant: Hiroaki Niimi , James Joseph Chambers
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Jacqueline J. Garner; Frederick J. Telecky, Jr.
- Main IPC: H01L21/336
- IPC: H01L21/336
Abstract:
The likelihood of forming silicon germanium abnormal growths, which can be undesirably formed on the gate electrode of a strained-channel PMOS transistor at the same time that silicon germanium source and drain regions are formed, is substantially reduced by using protection materials that reduce the likelihood that the gate electrode is exposed during the formation of the silicon germanium source and drain regions.
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