A method of forming PMOS transistors. A SiGe cavity formation process includes cavity etching a structure including a gate stack having a gate electrode on a gate dielectric on a substrate, a sidewall spacer, and a hardmask layer on the gate electrode. The cavity etching includes (i) a first anisotropic dry etch for etching through the hardmask layer lateral to the gate stack and beginning a recessed cavity in the substrate, (ii) a dry lateral etch, and (iii) a second anisotropic dry etch. A wet crystallographic etch completes formation of the recessed cavity. A customized time is calculated for a selected dry etch step from the plurality of dry etch steps based on in-process SiGe cavity data for a measured cavity parameter for a SiGe cavity formation process. The customized time for the selected dry etch is used to cavity etch at least one substrate in a lot or run.