Invention Grant
- Patent Title: Process for preparing a bonding type semiconductor substrate
- Patent Title (中): 制备接合型半导体衬底的方法
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Application No.: US13595284Application Date: 2012-08-27
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Publication No.: US08829488B2Publication Date: 2014-09-09
- Inventor: Kazuyoshi Furukawa , Yasuhiko Akaike , Shunji Yoshitake
- Applicant: Kazuyoshi Furukawa , Yasuhiko Akaike , Shunji Yoshitake
- Applicant Address: JP Kawasaki-shi
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Kawasaki-shi
- Agency: Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP11-162985 19990609; JP11-174138 19990621; JP2000-089754 20000328
- Main IPC: H01L23/06
- IPC: H01L23/06 ; H01L33/10 ; H01L33/00 ; H01L33/16 ; H01L21/18 ; H01L33/20

Abstract:
Provided is a laminate containing a first compound semiconductor layer; and a second compound semiconductor layer integrally bonded to the first compound semiconductor layer via a bonding layer. A plane A is in the second compound semiconductor layer bonded to a surface where a plane B is in the first compound semiconductor layer, or a surface where a plane B is in the second compound semiconductor layer bonded to a surface where a plane A in the first compound semiconductor layer. The impurity concentration of the bonding layer is 2×1018 cm3 or more.
Public/Granted literature
- US20130020681A1 PROCESS FOR PREPARING A BONDING TYPE SEMICONDUCTOR SUBSTRATE Public/Granted day:2013-01-24
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