Invention Grant
US08829574B2 Method and system for a GaN vertical JFET with self-aligned source and gate
有权
具有自对准源极和栅极的GaN垂直JFET的方法和系统
- Patent Title: Method and system for a GaN vertical JFET with self-aligned source and gate
- Patent Title (中): 具有自对准源极和栅极的GaN垂直JFET的方法和系统
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Application No.: US13334514Application Date: 2011-12-22
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Publication No.: US08829574B2Publication Date: 2014-09-09
- Inventor: Donald R. Disney , Isik C. Kizilyalli , Hui Nie , Linda Romano , Richard J. Brown , Madhan Raj
- Applicant: Donald R. Disney , Isik C. Kizilyalli , Hui Nie , Linda Romano , Richard J. Brown , Madhan Raj
- Applicant Address: US CA San Jose
- Assignee: Avogy, Inc.
- Current Assignee: Avogy, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Kilpatrick Townsend & Stockton LLP
- Main IPC: H01L29/808
- IPC: H01L29/808 ; H01L21/335 ; H01L29/66 ; H01L29/78
Abstract:
A semiconductor device includes a III-nitride substrate, a first III-nitride epitaxial layer coupled to the III-nitride substrate and having a mesa, and a second III-nitride epitaxial layer coupled to a top surface of the mesa. The semiconductor device further includes a III-nitride gate structure coupled to a side surface of the mesa, and a spacer configured to provide electrical insulation between the second III-nitride epitaxial layer and the III-nitride gate structure.
Public/Granted literature
- US20130161705A1 METHOD AND SYSTEM FOR A GAN VERTICAL JFET WITH SELF-ALIGNED SOURCE AND GATE Public/Granted day:2013-06-27
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