Invention Grant
US08829598B2 Non-volatile memory device having three dimensional, vertical channel, alternately stacked gate electrode structure
有权
具有三维，垂直沟道，交替堆叠的栅电极结构的非易失性存储器件
- Patent Title: Non-volatile memory device having three dimensional, vertical channel, alternately stacked gate electrode structure
- Patent Title (中): 具有三维，垂直沟道，交替堆叠的栅电极结构的非易失性存储器件
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Application No.: US13783681Application Date: 2013-03-04
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Publication No.: US08829598B2Publication Date: 2014-09-09
- Inventor: Se-Yun Lim , Sang-Hyun Oh , Gyo-Ji Kim , Eun-Seok Choi
- Applicant: SK hynix Inc.
- Applicant Address: KR Gyeonggi-do
- Assignee: SK Hynix Inc.
- Current Assignee: SK Hynix Inc.
- Current Assignee Address: KR Gyeonggi-do
- Agency: IP & T Group LLP
- Priority: KR10-2009-0052351 20090612; KR10-2010-0018724 20100302
- Main IPC: H01L29/792
- IPC: H01L29/792 ; H01L27/115 ; H01L29/66
Abstract:
A method for fabricating a non-volatile memory device, the method includes alternately stacking inter-layer dielectric layers and sacrificial layers over a substrate, etching the inter-layer dielectric layers and the sacrificial layers to form trenches to expose a surface of the substrate, etching the inter-layer dielectric layers exposed by the trenches to a predetermined thickness, forming junction layers over etched portions of the inter-layer dielectric layers, and burying a layer for a channel within the trenches in which the junction layers have been formed to form a channel.
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