Invention Grant
- Patent Title: Integrated circuits and transistor design therefor
- Patent Title (中): 集成电路及其晶体管设计
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Application No.: US13053604Application Date: 2011-03-22
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Publication No.: US08829602B2Publication Date: 2014-09-09
- Inventor: Werner Juengling
- Applicant: Werner Juengling
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Knobbe, Martens, Olson & Bear LLP
- Main IPC: H01L27/108
- IPC: H01L27/108

Abstract:
The invention includes a semiconductor structure having a gateline lattice surrounding vertical source/drain regions. In some aspects, the source/drain regions can be provided in pairs, with one of the source/drain regions of each pair extending to a digit line and the other extending to a memory storage device, such as a capacitor. The source/drain regions extending to the digit line can have the same composition as the source/drain regions extending to the memory storage devices, or can have different compositions from the source/drain regions extending to the memory storage devices. The invention also includes methods of forming semiconductor structures. In exemplary methods, a lattice comprising a first material is provided to surround repeating regions of a second material. At least some of the first material is then replaced with a gateline structure, and at least some of the second material is replaced with vertical source/drain regions.
Public/Granted literature
- US20110169063A1 INTEGRATED CIRCUITS AND TRANSISTOR DESIGN THEREFOR Public/Granted day:2011-07-14
Information query
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