Invention Grant
- Patent Title: Semiconductor package, package structure and fabrication method thereof
- Patent Title (中): 半导体封装,封装结构及其制造方法
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Application No.: US13563052Application Date: 2012-07-31
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Publication No.: US08829672B2Publication Date: 2014-09-09
- Inventor: Yan-Heng Chen , Jung-Pang Huang , Hsin-Yi Liao , Shih-Kuang Chiu , Guang-Hwa Ma
- Applicant: Yan-Heng Chen , Jung-Pang Huang , Hsin-Yi Liao , Shih-Kuang Chiu , Guang-Hwa Ma
- Applicant Address: TW Taichung
- Assignee: Siliconware Precision Industries Co., Ltd.
- Current Assignee: Siliconware Precision Industries Co., Ltd.
- Current Assignee Address: TW Taichung
- Agency: Edwards Wildman Palmer LLP
- Agent Peter F. Corless; Steven M. Jensen
- Priority: TW101111658A 20120402
- Main IPC: H01L21/56
- IPC: H01L21/56 ; H01L23/48 ; H01L21/02 ; H01L21/50 ; H01L21/60 ; H01L29/84 ; H01L23/34

Abstract:
A semiconductor package includes: a dielectric layer having opposite first and second surfaces; a semiconductor chip embedded in the dielectric layer and having a plurality of electrode pads; a plurality of first metal posts disposed on the electrode pads of the semiconductor chip, respectively, such that top ends of the first metal posts are exposed from the first surface; at least a second metal post penetrating the dielectric layer such that two opposite ends of the second metal post are exposed from the first and second surfaces, respectively; a first circuit layer formed on the first surface for electrically connecting the first and second metal posts; and a second circuit layer formed on the second surface for electrically connecting the second metal post. The semiconductor package dispenses with conventional laser ablation and electroplating processes for forming conductive posts in a molding compound, thereby saving fabrication time and cost.
Public/Granted literature
- US20130256875A1 SEMICONDUCTOR PACKAGE, PACKAGE STRUCTURE AND FABRICATION METHOD THEREOF Public/Granted day:2013-10-03
Information query
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