Invention Grant
- Patent Title: Semiconductor die having fine pitch electrical interconnects
- Patent Title (中): 具有细间距电互连的半导体管芯
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Application No.: US13243877Application Date: 2011-09-23
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Publication No.: US08829677B2Publication Date: 2014-09-09
- Inventor: Keith Lake Barrie , Suzette K. Pangrie , Grant Villavicencio , Jeffrey S. Leal
- Applicant: Keith Lake Barrie , Suzette K. Pangrie , Grant Villavicencio , Jeffrey S. Leal
- Applicant Address: US CA San Jose
- Assignee: Invensas Corporation
- Current Assignee: Invensas Corporation
- Current Assignee Address: US CA San Jose
- Agency: Lerner, David, Littenberg, Krumholz & Mentlik, LLP
- Main IPC: H01L23/28
- IPC: H01L23/28 ; H01L23/31 ; H01L21/68 ; H01L23/00 ; H01L25/065 ; H01L23/29

Abstract:
A die has interconnect pads on an interconnect side near an interconnect edge and has at least a portion of the interconnect side covered by a conformal dielectric coating, in which an interconnect trace over the dielectric coating forms a high interface angle with the surface of the dielectric coating. Because the traces have a high interface angle, a tendency for the interconnect materials to “bleed” laterally is mitigated and contact or overlap of adjacent traces is avoided. The interconnect trace includes a curable electrically conductive interconnect material; that is, it includes a material that can be applied in a flowable form, and thereafter cured or allowed to cure to form the conductive traces. Also, a method includes, prior to forming the traces, subjecting the surface of the conformal dielectric coating with a CF4 plasma treatment.
Public/Granted literature
- US20120248607A1 Semiconductor die having fine pitch electrical interconnects Public/Granted day:2012-10-04
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