In an integrated circuit having input circuitry whose positive and/or negative input signals are gated by one or more clocked input switches, the switch clock signal CLK_SW used to clock the input switch(es) is automatically generated based on the higher of the IC's power supply voltage VDD and the positive input signal voltage Vplus. In one embodiment, a clock level shifter shifts an input clock signal CLK_VDD from the VDD voltage domain to generate a level-shifted clock signal CLK_VPLUS in the Vplus voltage domain. Based on a control signal VSEL, a clock selector selects either the input clock signal or the level-shifted clock signal to be the switch clock signal. An over-voltage detector generates both the logic state and the voltage domain of the control signal based on the higher of VDD and Vplus, such that the input switches are appropriately clocked even during over-voltage conditions in which Vplus>VDD.