Invention Grant
US08830690B2 Minimizing plating stub reflections in a chip package using capacitance
有权
使用电容最小化芯片封装中的电镀短截线反射
- Patent Title: Minimizing plating stub reflections in a chip package using capacitance
- Patent Title (中): 使用电容最小化芯片封装中的电镀短截线反射
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Application No.: US12237444Application Date: 2008-09-25
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Publication No.: US08830690B2Publication Date: 2014-09-09
- Inventor: Bhyrav M Mutnury , Moises Cases , Nanju Na , Tae Hong Kim
- Applicant: Bhyrav M Mutnury , Moises Cases , Nanju Na , Tae Hong Kim
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agent Thomas E. Tyson; Jeffrey L. Streets
- Main IPC: H05K1/18
- IPC: H05K1/18 ; H05K1/02 ; H05K1/16 ; H05K3/24

Abstract:
Embodiments of the present invention are directed to shifting the resonant frequency in a high-frequency chip package away from an operational frequency by connecting a capacitance between an open-ended plating stub and ground. One embodiment provides a multi-layer substrate for interfacing a chip with a printed circuit board. A first outer layer provides a chip mounting location. A signal interconnect is spaced from the chip mounting location, and a signal trace extends from near the chip mounting location to the signal interconnect. A chip mounted at the chip mounting location may be connected to the signal trace by wirebonding. A plating stub extends from the signal interconnect, such as to a periphery of the substrate. A capacitor is used to capacitively couple the plating stub to a ground layer.
Public/Granted literature
- US20100073893A1 MINIMIZING PLATING STUB REFLECTIONS IN A CHIP PACKAGE USING CAPACITANCE Public/Granted day:2010-03-25
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