A control circuit is configured to, during an erase operation, set a voltage of a first line connected to a selected cell unit to a voltage larger than a voltage of a gate of a first transistor included in the selected cell unit by an amount of a first voltage; set a voltage difference between a voltage of a first line connected to an unselected cell unit and a voltage of a gate of a first transistor included in the unselected cell unit to a second voltage, the first and second voltages being different; apply in the selected and unselected cell units a third voltage to a gate of at least one of dummy transistors in a dummy memory string; and apply a fourth voltage to a gate of another one of the dummy transistors in the dummy memory string, the fourth voltage being lower than the third voltage.