A time-space switch in a ring architecture includes input circuitry including N links each receiving M timeslots, a two-dimensional matrix of a plurality of switching circuits, the two-dimensional matrix is configured to receive from the input circuitry each of the M timeslots from the N links in a pipelined manner, and output circuitry including N links configured to receive any of the M timeslots from any of the N links from the two-dimensional matrix. The input circuitry, the two-dimensional matrix, and the output circuitry are arranged in a ring architecture therebetween. A link encoding protocol method performed in electrical circuitry includes receiving a plurality of time slots, grouping the plurality of time slots into time slot groups, performing a cyclic redundancy check between adjacent time slot groups, 64/65B encoding the time slot groups, and forward error correction encoding a plurality of 65B codewords from the 64/65B encoding.