Invention Grant
- Patent Title: Delay detector circuit and receiver apparatus
- Patent Title (中): 延迟检测电路和接收装置
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Application No.: US13576809Application Date: 2010-07-08
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Publication No.: US08831152B2Publication Date: 2014-09-09
- Inventor: Naoki Umeda , Mituru Maeda
- Applicant: Naoki Umeda , Mituru Maeda
- Applicant Address: JP Osaka
- Assignee: Panasonic Corporation
- Current Assignee: Panasonic Corporation
- Current Assignee Address: JP Osaka
- Agency: Renner, Otto, Boisselle & Sklar, LLP
- Priority: JP2010-022671 20100204
- International Application: PCT/JP2010/004451 WO 20100708
- International Announcement: WO2011/096025 WO 20110811
- Main IPC: H03D1/00
- IPC: H03D1/00 ; H04L27/227 ; H04L7/04
Abstract:
The present invention provides a delay detector circuit that delivers performance at low cost and can reduce power consumption, and a receiver apparatus that uses this delay detector circuit. The delay detector circuit according to the present invention performs a part of decoding processing for decoding data transmitted by a transmitter apparatus based on a received wave of a two-phase modulation method. The receiver apparatus according to the present invention uses the delay detector circuit described above. Therefore the delay detector circuit and receiver apparatus of the present invention deliver performance at low cost and can reduce power consumption.
Public/Granted literature
- US20120294394A1 DELAY DETECTOR CIRCUIT AND RECEIVER APPARATUS Public/Granted day:2012-11-22
Information query
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