A pattern analysis method includes the steps of: grouping a plurality of polygons in a circuit layout into a plurality of polygon groups; locating a potential defect area of each polygon group according to an aerial image of the circuit layout; determining a representing point of the potential defect area of each polygon group; determining representing points of the plurality of polygons in each polygon group; and comparing a distribution pattern of the representing points of the plurality of polygons relative to the representing point of the potential defect area in one of the polygon groups with a distribution pattern of the representing points of the plurality of polygons relative to the representing point of the potential defect area in another of the polygon groups. The steps aforesaid are executed by a processor in a computer system.