Invention Grant
- Patent Title: Floating point multiplier circuit with optimized rounding calculation
- Patent Title (中): 具有优化舍入计算的浮点乘法器电路
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Application No.: US13247963Application Date: 2011-09-28
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Publication No.: US08832166B2Publication Date: 2014-09-09
- Inventor: Timothy David Anderson
- Applicant: Timothy David Anderson
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Robert D. Marshall, Jr.; Frederick J. Telecky, Jr.
- Main IPC: G06F7/00
- IPC: G06F7/00 ; H03K21/00 ; G06F7/483 ; H03K19/00 ; G06F1/32
Abstract:
An optimized floating point multiplier rounding circuit that minimizes the increase of the critical timing path of the calculation. The values of the temporary mantissa required to make the rounding decision are calculated simultaneously by the circuit shown in the invention.
Public/Granted literature
- US20120197954A1 FLOATING POINT MULTIPLIER CIRCUIT WITH OPTIMIZED ROUNDING CALCULATION Public/Granted day:2012-08-02
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